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Espressif Systems /ESP32-S2 /DEDICATED_GPIO /INTR_ST

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Interpret as INTR_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (GPIO0_INT_ST)GPIO0_INT_ST 0 (GPIO1_INT_ST)GPIO1_INT_ST 0 (GPIO2_INT_ST)GPIO2_INT_ST 0 (GPIO3_INT_ST)GPIO3_INT_ST 0 (GPIO4_INT_ST)GPIO4_INT_ST 0 (GPIO5_INT_ST)GPIO5_INT_ST 0 (GPIO6_INT_ST)GPIO6_INT_ST 0 (GPIO7_INT_ST)GPIO7_INT_ST

Description

Masked interrupt status

Fields

GPIO0_INT_ST

This is the status bit for DEDIC_GPIO0_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1.
GPIO1_INT_ST

This is the status bit for DEDIC_GPIO1_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1.
GPIO2_INT_ST

This is the status bit for DEDIC_GPIO2_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1.
GPIO3_INT_ST

This is the status bit for DEDIC_GPIO3_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1.
GPIO4_INT_ST

This is the status bit for DEDIC_GPIO4_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1.
GPIO5_INT_ST

This is the status bit for DEDIC_GPIO5_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1.
GPIO6_INT_ST

This is the status bit for DEDIC_GPIO6_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1.
GPIO7_INT_ST

This is the status bit for DEDIC_GPIO7_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data